Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors

Planar MOS devices miniaturization becomes quite challenging for transistors with reduced channel length due to the loss of gate control over the channel charges. As an alternative, multi-gate devices have been developed due to the better electrostatic control of the charges, which leads to a reduction of the short-channel effects [1-6]. However, for devices with extremely reduced channel length, it is needed the formation of ultra-sharp junctions with a high process complexity at source/channel and drain/channel interfaces. In order to address this issue, Junctionless Nanowire Transistors (JNTs) have been proposed [7-11] and have been the focus of several recent studies [12-18]. The JNT is a heavily-doped silicon nanowire surrounded by the gate stack. The doping distribution is constant from source to drain with the same doping element and concentration. Therefore, there are no doping gradients, eliminating impurity diffusion-related problems [7]. For an nMOS device an n-type element is used, whereas a p-type dopant is used in a pMOS device. The Junctionless transistor works similarly to an accumulation mode SOI device (AMSOI) [19]. For gate voltages (VG) lower than the threshold voltage (VTH), the silicon nanowire is fully depleted such that there is only a small drain current due to the diffusion of carriers. For gate voltages slightly higher than VTH, the current flows through drift in a neutral channel at the center of the device whereas for VG higher than the flatband voltage (VFB), the current flows through both an accumulation layer and bulk conduction. However, as stated by Kranti et al. [20], the JNT operates mainly in the partial depletion regime with a reduced electric field [21], while the AMSOI works most of time in accumulation regime with a higher electric field. Also, the bulk current in JNTs is higher than in the AMSOI owing to the heavier doping concentration. A schematic view of a triple-gate JNT is presented in Fig. 1, where the silicon nanowire heigth (H) and width (W), the gate oxide thickness (tox), the channel length (L) and the buried oxide thickness (tBox) are indicated. abstraCt1